1. Field of the Invention
The principles of the present invention relate in general to ferroelectric memories, and in particular, but not by way of limitation, to a device and method for reading ferroelectric memory cells in a non-destructive readout manner.
2. Description of Related Art
It is well known that ferroelectric materials are capable of retaining polarization which can be used to store information in a non-volatile memory. For example, if a strong enough electric field or voltage is placed across a ferroelectric capacitor, when the voltage is removed, a polarization in the direction of the electric field remains. If the electric field is then placed across the same capacitor in the opposite direction, the ferroelectric material switches, and when the field is removed, a polarization in the opposite direction remains. Electronic circuits have been designed to associate the polarization in one direction with a logic “1” state, and polarization in the opposite direction with a logic “0” state. See, for example, the circuits described in the U.S. Pat. No. 2,876,436 issued Mar. 3, 1959 to J. R. Anderson.
As with other integrated circuit memories, these circuits include memory cells arranged in rows and columns, where each memory cell includes at least one switch and a capacitor having a pair of electrodes. The memory cells also include plate lines, sometimes referred to as drive lines, connected to one electrode of the capacitor in each cell, and bit lines connected to the other electrode of the capacitor through the switch. In the Anderson patent cited above, the switch is a diode. As known in the art, the switch can be a transistor having a gate, a source and a drain. The memory includes word lines connected to the control gate of the transistor. See, for example, U.S. Pat. No. 4,873,664 issued Oct. 10, 1989 to S. Sheffield Eaton, Jr. The transistor acts as a switch controlled by its gate to connect the capacitor to the bit line. Information is written into a memory cell by placing either a high or a low voltage on the bit line, turning the transistor ON to connect the bit line to the capacitor of the memory cell and placing a predetermined voltage between the high and low voltage on the drive line. The high voltage causes the memory cell to assume one polarization state, and the low voltage causes the memory cell to assume the opposite polarization state. The memory cell is read by creating a voltage difference between the bit line and drive line, and connecting the bit line to the capacitor via the transistor. If the ferroelectric state changes due to the applied voltage, the bit line will assume a first voltage, and if the ferroelectric state does not switch, then the bit line will assume a second voltage. The bit line voltage is compared to a reference voltage that is about half-way between the first and second voltages; if the bit line voltage is below the reference voltage, a sense amp drives an output low, and if the bit line voltage is above the reference voltage, a sense amp drives an output high. In this way, the state of the ferroelectric capacitor prior to reading determines the output state when the cell is read.
In the above-described memory and other similar conventional ferroelectric memories, the drive line is pulsed with a high logic voltage level. The drive line, being relatively long and connected to the electrodes of many capacitors, has a high capacitance. Thus, it takes a relatively long time for the voltage to rise to its full value, thereby resulting in a long reading and writing time to the memory. To speed up the read and write processes, ferroelectric memories in which the drive line is not pulsed have been developed. See Hiroki Koike et al., “A 60-ns 1 Mb Nonvolatile Ferroelectric Memory With A Nondrive Cell Plate Line Write/Read Scheme” IEEE Journal of Solid State Circuits, Vol. 31, No. 11, November 1996. Another solution has been to make the drive line parallel to the bit line, so that only one ferroelectric memory cell of a matrix of memory cells at a time is pulsed. See the embodiment of FIG. 6 in the Eaton, Jr. patent mentioned above. Segmented drive lines have also been proposed to speed up the drive line cycle and reduce power. See U.S. Pat. No. 5,598,366. However, all these memories have not been successful due to significant disturb problems. “Disturb” is a problematic feature of most prior art ferroelectric memories in which “disturb” voltages, usually small in amplitude, are unavoidably applied to non-accessed memory cells, which voltages can change the memory state and thus lead to erroneous readings. For example, in the Koike et al. reference, it is explained that leakage from the bit line and drive line to the nodes of a capacitor that is not accessed can destroy the data. This problem is overcome with a compensation scheme which adds complexity to the memory and slows it down. Thus, the disturb problem has either resulted in memories that have been made more complex and slower to overcome the disturb, as in the Koike et al. reference, or simply have resulted in the design being too unreliable to be successful, such as the Eaton, Jr. patent.
Various ferroelectric materials are known, such as Phase III potassium nitrate, bismuth titanate and the PZT family of lead zirconate and titanate compounds, for example. One characteristic of such materials is a hysteresis curve or loop of the sort illustrated in FIG. 1, where the abscissa represents the field voltage applied to the material and the ordinate represents the polarization of the material. Because of the hysteresis curve, if a capacitor is formed using a ferroelectric material between its plates, the flow of current through the capacitor will depend on the prior history of the voltages applied to the device. Briefly, if a ferroelectric capacitor is in an initial state and zero volts is applied, it may have a polarization indicated at point A in FIG. 1. A physical characteristic of the device will be its so called “coercive voltage” represented by a dashed line B. If a positive voltage greater than the coercive voltage B is applied across the capacitor, then the capacitor will conduct current and move to a new polarization represented by point C. When the voltage is brought to zero, rather than returning to the polarization represented at A, the ferroelectric capacitor instead will maintain essentially the same polarization, as indicated at point D. A further positive voltage will cause relatively little change in the polarization, moving it toward or beyond point C. However, a substantial enough negative voltage will cause the polarization to vary as represented by point E. Thereafter, when such negative voltage is removed from the capacitor, the polarization of the device remains essentially the same and moves to point A. Thus, points A and D represent two states occurring at zero volts applied across the capacitor, but depend on the history of voltage applied to the device.
Consequently, a ferroelectric capacitor is usable as part of a memory cell. Point A can represent a logic “0,” and point D can represent a logic “1.” To determine the state of a ferroelectric capacitor, a voltage pulse may be applied and the current which follows be sensed to thereby determine the state. To write into a ferroelectric capacitor cell, a positive or negative voltage is applied to the plates of the capacitor, which causes the ferroelectric material to move along its hysteresis curve as shown in FIG. 1, forcing it into a stable state corresponding to the data, a logic “1” or “0.” To read from a ferroelectric memory cell, if a positive pulse having a logic high voltage level is applied and relatively little current is drawn or charge moved by the capacitor, then this indicates that the capacitor is in state D. If substantial charge moves, this indicates that the capacitor is in state A.
It will be appreciated that if a read operation occurs and a significant amount of charge moves to cause the capacitor to move from one stable state to the other along with the hysteresis curve, then the data within the cell is flipped, as the cell moves to the opposite stable state that represents the opposite binary digit. This reading operation causes destruction of the content of the ferroelectric memory cell and is appropriately called destructive readout. Restoration of the data is usually utilized when reading a memory cell using a ferroelectric capacitor as the memory element. However, restoration consumes time and power.
FIG. 2 is a schematic of a conventional ferroelectric memory cell 200 having a 1T1C configuration, as provided by U.S. Pat. No. 4,873,664 by Ramtron Corp. The memory cell includes a ferroelectric capacitor Cf and MOSFET transistor M1. A bit line BL is coupled to a source terminal S of the transistor M1 and one plate of the capacitor Cf is coupled to a drain terminal D of the transistor M1. A word line is coupled to a gate terminal G of the transistor M1 for controlling operation thereof. A plate line PL is coupled to a second plate of the capacitor Cf.
FIGS. 3A and 3B are timing diagrams showing timing signals for writing to the conventional ferroelectric memory cell 200 of FIG. 2. FIG. 3A provides timing signals to write a logic “1” to the memory cell 200 by turning the bit line BL high while the word line WL is high to turn on the MOSFET M1 and the plate line PL remains low. To change the polarity of the ferroelectric capacitor Cf, FIG. 3B shows that the plate line PL is turned high while the word line WL is high and the bit line BL remains low.
FIG. 3C is a timing diagram showing timing signals for reading data stored in memory cell 200. The data is read out by turning the word line WL high to turn the MOSFET transistor ON and applying a voltage on the plate line PL. Depending on the value of the data stored in the capacitor Cf, a voltage level applied to the bit line BL increases or decreases. Typically, the voltage level applied to the plate line PL is high (e.g., 3V) to guarantee that enough voltage difference is applied to the bit line BL to differentiate between a logic “0” and “1” stored in the capacitor Cf. As understood in the art, when a voltage level above the coercive voltage (e.g., 1.0V) is applied to a ferroelectric capacitor Cf, data being stored in the capacitor Cf is destroyed. This read operation is called destructive readout (DRO).
What is needed is a circuit and process for reading the data stored in a ferroelectric memory cell that utilizes a non-destructive readout (NDRO) technique.